In fabricating a flash memory device of less than 0.18 μm, one important factor is the area of a floating gate where electrons are built up. In related prior art processes of fabricating a flash memory device, a hard mask and oxide spacer structure is used to overcome the difficulties of forming a fine pattern, and thus the process becomes very complicated.
Hereinafter, a related prior art method of fabricating a floating gate of a flash memory device will be described with reference to FIGS. 1A to 1E.
FIGS. 1A to 1E are sectional views illustrating a prior art method of fabricating a floating gate of a flash memory device.
As illustrated in FIG. 1A, a tunneling oxide layer 12, which is 80 Å to 120 Å thick, is formed on a semiconductor substrate 11. A poly silicon layer 13a for a floating gate, which is 900 Å to 1100 Å thick, is formed on the tunneling oxide layer 12.
As illustrated in FIG. 1B, a first oxide layer 14, which is 2000 Å to 2500 Å thick, is formed on the poly silicon layer 13a, and a photoresist 15 is applied on the first oxide layer 14. Then, the photoresist 15 is selectively patterned to define a floating gate region using an exposure and development process.
After the photoresist 15 is applied, an anti-reflective layer (not shown), which is 600 Å thick, can be formed on the photoresist 15.
Next, the first oxide layer 14 is selectively patterned using the patterned photoresist 15 as a mask.
As illustrated in FIG. 1C, the photoresist 15 is removed, and then a cleaning process is performed on the semiconductor substrate 11 to remove any remaining photoresist 15.
Then, a second oxide layer, which is 650 Å to 850 Å thick, is formed on the entire surface of the semiconductor substrate 11 and first oxide layer 14. An etch back process of the second oxide layer is performed to form the second oxide layer sidewalls 16 on the sides of the first oxide layer 14.
As illustrated in FIG. 1D, using the first oxide layer 14 and the second oxide layer sidewalls 16 as a hard mask, the poly silicon layer 13a is selectively etched to form a floating gate 13.
Here, the floating gate 13 has a width broader than that of the floating gate region defined by the patterned photoresist 15.
As illustrated in FIG. 1E, a wet etching process is performed to remove the first oxide layer 14 and the second oxide layer sidewall 16. Then, subsequent processes can be performed.
When space less than 100 nm can be patterned on the poly silicon layer 13a through the photoresist pattern, the hard mask process is unnecessary. However, it is not possible to form a fine pattern less than 100 nm in the prior art photo process discussed above so a fine pattern less than 100 nm is formed using the hard mask such as an oxide layer.
Once the fine pattern is formed, the oxide layer used as the hard mask is removed through a wet process. At this point, productivity is decreased and product characteristics are deteriorated due to the various defects.